`timescale 1ns/1ps

module top;
  reg clk1, rst_n;
  reg clk2;
  reg [31:0] data1;
  reg [31:0] data2;
  always #5 clk1=~ clk1;

always @(posedge clk1 or negedge rst_n) begin
if (rst_n == 1'b0)
    clk2 <= 1'b0;
else
    clk2 <= ~clk2;
end

always @(posedge clk1 or negedge rst_n) begin
if (rst_n == 1'b0)
    data1 <= 8'd0;
else begin
    data1 <= data1 + 8'd1;
    $display("**** data1 is %0d ****", data1);end

end

always @(posedge clk2) begin
  data2 <= data1;
  $display("===== data2 is %0d ====", data2);
end

  initial begin
    clk1 = 0;
    rst_n = 0;
    #20;
    rst_n = 1;
    #1000;
    $finish;
  end

  initial begin
    $fsdbDumpfile("test_top");
    $fsdbDumpvars;
  end


endmodule

